Manufacturers of integrated circuit devices often form on a single silicon wafer numerous separate integrated circuits. The silicon wafer is then cut into integrated circuit devices, commonly referred to as "chips." The chips may be packaged either separately or as part of a multi-chip module for further connection to other electronic and electrical devices. For any such chip, numerous exposed interconnects form important communication paths between the chips and other devices.
One type of integrated circuit device that uses numerous interconnects has the name of a "flip chip" device due to its packaging orientation being flipped or inverted when compared to more traditional chip packaging designs. Part of the flip chip device packaging process is to bond its interconnects with a corresponding wiring pattern on a substrate. One approach to bonding flip chip device interconnects to the substrate entails their "cold" or low temperature compression into the substrate.
In bonding flip chip devices to substrates by compression, it is necessary to determine the minimum amount of compressive force. As the number of interconnects have increased due to circuit components becoming smaller and more compact, packaging requirements have changed. For example, an increasing number of interconnects requires that the amount of force that the flip chip device receives must increase in order for each interconnect to receive its necessary allotment of the total compressive force. An increased number of interconnects also mandates improved alignment and placement of the flip chip interconnects with the corresponding wiring pattern of the substrate. In addition, more interconnects per unit area requires a more even distribution of the bonding force across the flip chip device surface. For example, in an increasing number of instances as much as 100 pounds of precisely aligned, evenly distributed force is necessary to bond the interconnects of a flip chip device. As circuit densities increase so that placement accuracy requirements fall below the three micron regime and into the one micron regime and below, the requirement for placement accuracy becomes even more important.
Known high force compression force flip chip bonding methods and systems cannot achieve this degree of accuracy and uniformity at these high pressures. In these approaches to flip chip interconnect bonding, not only is the total force a problem, but also these systems have inherent displacement or misalignment problems. No present system for high force compression flip chip bonding overcomes these limitations.
Consequently, there is a need for a high force compression force flip chip bonding method and system that can reach 100 pounds force and beyond (e.g., 300 pounds), as well as satisfy placement alignment tolerances associated with interconnects for circuit densities of three microns and below.
There is yet a further need for a high force compression force bonding method and system for flip chip devices that avoid lateral (horizontal) shifting during compression such as that which occurs in conventional high force compression bonding methods and systems.
There is a further need for a method and system of high force compression bonding for flip chip devices that distribute the compression force uniformly across the flip chip device so that all interconnects in the same plane receive a relatively equal amount of the compression force.